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approximate scale figure 1. typical circuit with separate power supply to transformer figure 2. typical circuit with single power supply to igbt gate cout v out d1 t1 r1 r2 r3 3.0 to 5.5 v v bias cin 4.7 f c1 0.1 f 100 k 7 150 k 7 150 k 7 r4 1.20 k 7 charge gnd fb sw trigger igbtdrv done vin A8835 A8835-ds, rev. 1 description the A8835 is a highly integrated ic that charges photoflash capacitors for digital and film cameras. an integrated mosfet switch drives the transformer in a flyback topology. it also features an integrated igbt driver that facilitates the flash discharge function and saves board space. the charge pin enables the A8835 and starts the charging of the output capacitor. when the designated output voltage is reached, the A8835 stops the charging until the charge pin is toggled again. the d o n e pin is an open-drain indicator of when the designated output voltage is reached. the peak current limit can be adjusted to eight different levels between 550 ma and 1.75 a, by clocking the charge pin. this allows the user to operate the flash even at low battery voltages. the A8835 can be used with two alkaline/nimh/nicad or one single-cell li+ battery connected to the transformer primary. connect the vin pin to a 3.0 to 5.5 v supply, which can be either the system rail or the li+ battery, if used. the A8835 is available in a very low profile (0.75 mm) 10-contact 3 mm 3 mm tdfn package, making it ideal for space-constrained applications. it is lead (pb) free, with 100% matte-tin leadframe plating and has an exposed pad for enhanced thermal dissipation. features and benefits ? eight-level, digitally-programmable current limits from 550 ma to 1.75 a ? voltage sensing feedback before output diode for low leakage ? no external pull-down resistors needed ? power with 1 li+ or 2 alkaline/nimh/nicad batteries ? low quiescent current draw (1 a max in shutdown mode) ? zero-voltage switching for lower loss ? adjustable output voltage ? integrated igbt driver with trigger ? charge complete indication ? >75% efficiency ? low-profile (0.75 mm high) 3 mm 3 mm tdfn 10-contact package photoflash capacitor charger with programmable current limit and igbt driver package: 10-contact tdfn with exposed thermal pad (suffix ej) applications: typical applications A8835 ? digital camera flash ? film camera flash ? cell phone flash ? emergency strobe light + to igbt gate v out d1 t1 r1 r2 n =10.2 r3 100 k 7 150 k 7 1.20 k 7 1% 1% 150 k 7 1% r4 v batt 1.5 to 5.5 v v bias 3.0 to 5.5 v cin 4.7 f cout 100 f 330 v c1 0.1 f A8835 charge gnd fb sw trigger igbtdrv done vin
photoflash capacitor charger with programmable current limit and igbt driver A8835 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com selection guide part number package packing* A8835eejtr-t 10-pin tdfn 1500 pieces/ 7-in. reel *contact allegro for additional packing options absolute maximum ratings characteristic symbol notes rating units sw pin v sw dc voltage. (v sw is self-clamped by an internal active clamp and is allowed to exceed 40 v dur- ing flyback spike durations. maximum repetitive energy during flyback spike: 0.5 j at frequency 400 khz.) ?0.3 to 40 v igbtdrv pin v igbtdrv ?0.3 to v in + 0.3 v fb pin v fb ?0.3 to v in v all other pins v x ?0.3 to 7 v operating ambient temperature t a range e ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc package thermal characteristics characteristic symbol test conditions* rating units package thermal resistance r ja on 4-layer pcb, based on jedec standard 45 oc/w *additional information is available on the allegro website.
photoflash capacitor charger with programmable current limit and igbt driver A8835 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional block diagram vin v in sw charge gnd cmp2 done fb q i lim decoder adjustable reference igbtdrv trigger 40 v dmos q q set clr s r q q set clr s r cmp1 1.2 v i lim comparator h m l triggered timer control logic enable 18 s one-shot dcm detector (dv/dt = 0) 100 k 100 k 20 k terminal list table 10 9 8 7 6 nc fb pad done trigger sw 1 2 3 4 5 nc igbtdrv vin gnd charge device pin-out diagram number name function 1,10 nc no connection. 2 igbtdrv igbt driver gate drive output. 3 vin input voltage. connect to 3 to 5.5 v bias supply. decouple v in voltage with 0.1 f ceramic capacitor placed close to this pin. 4 gnd device ground 5 charge charge enable and current limit serial programming pin. set this pin low to shut down the chip. 6sw drain connection of internal dmos switch. connect to trans- former primary winding. 7 trigger strobe signal input 8 d o n e open collector output, pulls low when output reaches target value and charge is high. goes high during charging or when- ever charge is low. 9 fb output voltage feedback ?pad exposed pad for enhanced thermal dissipation. connect to ground plane.
photoflash capacitor charger with programmable current limit and igbt driver A8835 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics valid at v in = 3.3 v, t a = 25c except indicates specifications guaranteed from ? 40c to 85c ambient, unless otherwise specified characteristics symbol test conditions min. typ. max. units supply voltage* v in 3 ? 5.5 v uvlo enable threshold v uvlo v in rising 2.55 2.65 2.75 v uvlo hysteresis v uvlohys ? 150 ? mv supply current i in charging ? 1.5 ? ma charging done ? 1 10 a shutdown (v charge = 0 v, v trigger = 0 v) ? 0.01 1 a primary side current limit (ilim clock input at charge pin) i swlim1 1.58 1.75 1.93 a i swlim2 ? 1.58 ? a i swlim3 ? 1.4 ? a i swlim4 ? 1.22 ? a i swlim5 ? 1.05 ? a i swlim6 ? 0.86 ? a i swlim7 ? 0.7 ? a i swlim8 ? 0.55 ? a sw on resistance r ds(on)sw v in = 3.3 v, i d = 800 ma ? 0.27 ? sw leakage current* i swlkg v sw = 35 v ??1 a switch off timeout t off(max) ?18? s switch on timeout t on(max) ?18? s charge input current i charge v charge = v in ?33? a charge input voltage* v charge(h) 2??v v charge(l) ? ? 0.8 v ilim clock high time at charge pin t ilim1(h) initial pulse 20 ? ? s t ilim(h) subsequent pulses 0.2 ? ? s ilim clock low time at charge pin t ilim(l) 0.2 ? ? s total ilim setup time t ilim(su) ?54? s d o n e output leakage current* i donelkg ??1 a d o n e output low voltage* v done(l) 32 a into d o n e pin ? ? 100 mv fb voltage threshold* v fb 1.187 1.205 1.223 v fb input current i fb v fb = 1.205 v ? ?120 ? na igbt driver igbtdrv on resistance to vin r ds(on)i-v v in = 3.3 v, v igbtdrv = 1.5 v, v trigger = v in ?5? igbtdrv on resistance to gnd r ds(on)i-g v in = 3.3 v, v igbtdrv = 1.5 v, v trigger = 0 v ? 6 ? trigger input current i trigger v trigger = v in ?33? a trigger input voltage* v trigger(h) 2??v v trigger(l) ? ? 0.8 v propagation delay, rising t dr r gate =12 , c load = 6500 pf, v in = 3.3 v ? 30 ? ns propagation delay, falling t df r gate =12 , c load = 6500 pf, v in = 3.3 v ? 30 ? ns output rise time t r r gate =12 , c load = 6500 pf, v in = 3.3 v ? 70 ? ns output fall time t f r gate =12 , c load = 6500 pf, v in = 3.3 v ? 70 ? ns dv/dt threshold for zvs comparator dv/dt measured at sw pin ? 20 ? v/ s *specification over the range t a = ?40c to 85c guaranteed by design and characterization.
photoflash capacitor charger with programmable current limit and igbt driver A8835 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com operation timing diagram explanation of events: a. start charging by pulling charge to high, provided that v in is above the v uvlo level. b. charging stops when v out reaches the target voltage. d o n e goes low, to signal the completion of the charging process. c. start a new charging process with a low-to-high transition at the charge pin. d. pull charge to low, to put the controller in low-power standby mode. e. charging does not start, because v in is below v uvlo level when charge goes high. f. after v in goes above v uvlo , another low-to-high transition at the charge pin is required to start charging. v out charge vin v uvlo target v out trigger igbtdrv sw ab cdef done igbtdrv trigger t dr t r t df t f 50% 10% 90% 50% 10% 90% igbt drive timing definition
photoflash capacitor charger with programmable current limit and igbt driver A8835 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com rising signal igbt drive performance symbol parameter units/division c2 v igbtdrv 1 v c3 v trigger 1 v t time 50 ns conditions parameter value t dr 22.881 ns t r 63.125 ns c load 6800 pf r gate 12 c3 c2 t v igbtdrv v trigger falling signal symbol parameter units/division c2 v igbtdrv 1 v c3 v trigger 1 v t time 50 ns conditions parameter value t df 27.427 ns t f 65.529 ns c load 6800 pf r gate 12 t r v igbtdrv v trigger t c3 c2 t f performance characteristics igbt drive waveforms are measured with r-c load (12 , 6800 pf)
photoflash capacitor charger with programmable current limit and igbt driver A8835 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com overview the A8835 is a photoflash capacitor charger control ic with adjustable input current limiting. it also integrates an igbt driver for strobe operation of the flash tube, dramatically saving board space in comparison to discrete solutions for strobe flash operation. the control logic is shown in the functional block diagram. the charging operation of the A8835 is started by a low-to-high signal on the charge pin, provided that v in is above v uvlo level. it is strongly recommended to keep the charge pin at logic low during power-up. when v in exceeds the uvlo level, a low-to-high transition on the charge pin is required to start the charging. the primary peak current is set by input program- ming signals from the charge pin. when a charging cycle is initiated, the transformer primary side current, i primary , ramps up linearly at a rate determined by the combined effect of the battery voltage, v batt , and the primary side inductance, l primary . when i primary reaches the current limit, i swlim , the internal mosfet is turned off immediately, allowing the energy to be pushed into the photoflash capacitor, c out , from the secondary winding. the secondary side current drops linearly as c out charges. the switching cycle starts again, either after the transformer flux is reset, or after a predetermined time period, t off(max) (18 s), whichever occurs first. the output voltage, v out , is sensed by a resistor string, r 1 , r 2 , and r 3 (see application circuit diagrams), connected across the transformer secondary winding. this resistor string forms a volt- age divider that feeds back to the fb pin. the resistors must be sized to achieve a desired output voltage level based on a typical value of 1.205 v at the fb pin. as soon as v out reaches the desired value, the charging process is terminated. toggling the charge pin can start a refresh operation. input current limiting the peak current limit can be programmed to eight different lev- els, from 1.75 a down to 550 ma, by clocking the charge pin. an internal digital circuit decodes the input clock signals, which sets the switch current limit. this flexible scheme allows the user to operate the flash circuit according to different battery input voltages. the battery life can be effectively extended by setting a lower current limit at low battery voltages. figure 4 shows the ilim clock timing scheme protocol. the total ilim setup time, t ilim(su) , denotes the time needed for the decoder circuit to receive ilim inputs and set i swlim . apply cur- rent limit pulses during t ilim(su) (54 s) period. figure 5 shows the timing definition of the primary current limiting circuit. at the end of the setup period, t ilim(su) , primary current starts to ramp up to the set i swlim . the i swlim setting remains in effect as long as the charge pin is high. to reset the ilim counter, pull the charge pin low before clocking in the new setting. functional description clock input at charge pin 0 s20 s 54 s first rising edge subsequent rising edges (0 to 7) t ilim(su) = ilim setup time t ilim1(h) = first pulse width t ilim(l) 0.2 s t ilim(h) 0.2 s switching starts figure 4. ilim clock timing definition charge 0 s 54 s switching starts i sw start ilim counter 20 s switching stops i swlim4 = 1.22 a reset ilim counter four rising edges within t ilim(su) figure 5. current limit programming example (i swlim4 selected).
photoflash capacitor charger with programmable current limit and igbt driver A8835 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com after the first start-up or an ilim decoder reset, each new current limit can be set by sending a burst of pulses to the charge pin. the first rising edge starts the ilim decoder, and up to 8 ris- ing edges will be counted to set the i swlim level. the first pulse width, t ilim1(h) , must be at least 20 s long. subsequent pulses (up to 7 more) can be as short as 0.2 s. the last low-to-high edge must arrive within 54 s from the first edge. the charge pin will stay high afterwards. switch on-time and off-time control the A8835 implements an adaptive on-time/off-time control. on- time duration, t on , is equal to t on = i swlim l p / v bat . off-time duration, t off , depends on the operating conditions during switch off-time. the A8835 applies its two charging modes, fast charg- ing mode and timer mode, according to those conditions. timer mode and fast charging mode the A8835 achieves fast charging times and high efficiency by operating in discontinuous conduction mode (dcm) through most of the charging process the relationship of timer mode and fast charging mode is shown in figure 4. the ic operates in timer mode when beginning to charge a com- pletely discharged photoflash capacitor, usually when the output voltage, v out , is less than approximately 15 to 20 v. timer mode is a fixed period, 18 s, off-time control. one advantage of hav- ing timer mode is that it limits the initial battery current surge and thus acts as a ?soft-start.? a time-expanded view of a timer mode interval is shown in figure 5. as soon as a sufficient voltage has built up at the output capaci- tor, the ic enters fast-charging mode. in this mode, the next switching cycle starts after the secondary side current has stopped flowing, and the switch voltage has dropped to a minimum value. a proprietary circuit is used to allow minimum-voltage switch- ing, even if the sw pin voltage does not drop to 0 v. this enables fast-charging mode to start earlier, thereby reducing the overall charging time. minimum-voltage switching is shown in figure 6. during fast-charging mode, when v out is high enough (over 50 v), true zero-voltage switching (zvs) is achieved. this further improves efficiency as well as reduces switching noise. a zvs interval is shown in figure 7. figure 7. zvs voltage switching: v out = 120 v, t =0.2 s/div, v bat = 3.6 v, i swlim = 1.05 a. figure 4. timer mode and fast charging mode: t = 200 ms/div; v out = 50 v/div; v bat = 1 v/div.; i in = 100 ma/div., v bat = 3.6 v; c out = 20 f / 330 v; and i swlim 0.7 a. figure 5. expanded view of timer mode: v out 14 v; t = 2 s/div; v bat = 3.6 v; i swlim = 1.05 a. figure 6. minimum-voltage switching: v out 15 v; t =1 s/div; v bat = 3.6 v; and i swlim = 1.05 a. i sw v bat v out v sw i sw v bat v out v sw i sw v bat v out v sw i sw v bat v out v sw timer mode fast charging mode i in v bat v out
photoflash capacitor charger with programmable current limit and igbt driver A8835 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com transformer design turns ratio. the minimum transformer turns ratio, n, (second- ary : primary) should be chosen based on the following formula: v batt v d _ drop v out n ? + 40 (1) where: v out (v) is the required output voltage level, v d_drop (v) is the forward voltage drop of the output diode(s), v batt (v) is the transformer battery supply, and 40 (v) is the rated voltage for the internal mosfet switch, representing the maximum allowable reflected voltage from the output to the sw pin. for example, if v batt is 3.5 v and v d_drop is 1.7 v (which could be the case when two high voltage diodes were in series), and the desired v out is 320 v, then the turns ratio should be at least 8.9. in a worst case, when v batt is highest and v d_drop and v out are at their maximum tolerance limit, n will be higher. taking v batt = 5.5 v, v d_drop = 2 v, and v out = 320 v 102 % = 326.4 v as the worst case condition, n can be determined to be 9.5. in practice, always choose a turns ratio that is higher than the calculated value to give some safety margin. in the worst case example, a minimum turns ratio of n = 10 is recommended. primary inductance . as a loose guideline when choosing the primary inductance, l primary ( h), use the following formula: swlim i n v out primary l 9 10 300 ? . (2) ideally, the charging time is not affected by transformer primary inductance. in practice, however, it is recommended that a primary inductance be chosen between 10 h and 20 h. when l primary is lower than 10 h, the converter operates at higher fre- quency, which increases switching loss proportionally. this leads to lower efficiency and longer charging time. when l primary is greater than 20 h, the rating of the transformer must be dra- matically increased to handle the required power density, and the series resistances are usually higher. a design that is optimized to achieve a small footprint solution would have an l primary of 12 to 14 h, with minimized leakage inductance and secondary capaci- tance, and minimized primary and secondary series resistance. see the table recommended components for more information. leakage inductance and secondary capacitance the transformer design should minimize the leakage inductance to ensure the turn-off voltage spike at the sw node does not exceed the 40 v limit. an achievable minimum leakage induct- ance for this application, however, is usually compromised by an increase in parasitic capacitance. furthermore, the transformer secondary capacitance should be minimized. any secondary capacitance is multiplied by n 2 when reflected to the primary, leading to high initial current swings when the switch turns on, and to reduced efficiency. input capacitor selection ceramic capacitors with x5r or x7r dielectrics are recom- mended for the input capacitor, cin. during initial timer mode the device operates with 18 s off-time. a typical input section for a photoflash module with input filter inductor, or a test setup with long connecting wires is shown in figure 12. the resonant period caused by input filter inductor and capacitor should be at least 2 times greater or smaller than the 18 s timer period, to reduce input ripple current during this period. see figure 13. applications information + c in A8835 v bat l in figure 12. typical input section with input inductance (inductance, l in , may be an input filter inductor or inductance due to long wires in test setup) figure 13. effects of changing the values of c in . c in = 4.7 f v out i vin c in = 10 f v out i vin
photoflash capacitor charger with programmable current limit and igbt driver A8835 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com the resonant period is given by: t res = 2 ( l in c in ) ? it is recommended to use at least 4.7 f / 6.3 v to decouple the battery input, v bat , at the primary of the transformer. decouple the v in pin using a 0.1 f / 6.3 v bypass capacitor. output diode selection choose the rectifying diode(s), d1, to have small parasitic capaci- tance (short reverse recovery time) while satisfying the reverse voltage and forward current requirements. the peak reverse voltage of the diode, v dpeak , occurs when the internal mosfet switch is closed. it can be calculated as: v dpeak = v out + n v bat the peak current of the rectifying diode, i dpeak , is calculated as: i dpeak = i primarypeak / n layout guidelines key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). use short, thick traces for connections to the transformer primary and sw pin. it is important that the d o n e signal trace and other signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. in addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board. avoid locating the ground plane underneath transformer second- ary and diode to minimize parasitic capacitance. it is recommended to use a single high voltage resistor to sense output voltage. two series resistors, r1 and r2, may be used on the high voltage v out side. referring to figure 17, a parasitic capacitor, cp1, across the r1-r2 junction and gnd, can affect output voltage accuracy due to slow voltage sensing at the fb pin. a parasitic capacitor, cp2, between the r1-r2 junction and v out , can affect output voltage accuracy due to overshoot in the sensed voltage at the fb pin. very small capacitance ( 1 pf) can cause a significant error. figure 14. input current waveforms with li+ battery connected by 5-in. wire and decoupled by 4.7 f capacitor. t = 500 ms/div; v bat = 2 v/div; v out = 100 v/div.; i bat = 1 a/div. figure 16. input current waveforms with li+ battery connected through 10 h inductor and 10 f capacitor. t = 500 ms/div; v bat = 2 v/div; v out = 100 v/div.; i bat = 500 ma/div. figure 15. input current waveforms with li+ battery connected through 10 h inductor and 4.7 f capacitor. t = 500 ms/div; v bat = 2 v/div; v out = 100 v/div.; i bat = 1 a/div. v bat i bat v out v bat i bat v out v bat i bat v out
photoflash capacitor charger with programmable current limit and igbt driver A8835 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com minimize parasitic capacitors with careful layout. the center pad between r1 and r2 should be routed away from any gnd and other traces. avoid placing the gnd plane directly underneath the center pad. place r1 and r2 as close as possible in a straight line as shown in figure 18. v out d1 + r1 r2 r3 cout cp1 cp2 A8835 fb sw figure 17. equivalent circuit with parasitic capacitors across feedback divider. figure 18. recommended layout for feedback divider. r1 r2 r3 fb gnd do not locate areas of the gnd plane underneath this zone
photoflash capacitor charger with programmable current limit and igbt driver A8835 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com recommended layout r5 xenon + r4 charge charge pad cout c3 d1 x2 c4 q1 A8835 nc nc fb vin vin igbtdrv done done trigger trigger sw gnd xenon trigger xenon ? rg1 r3 r2 r1 cin
photoflash capacitor charger with programmable current limit and igbt driver A8835 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com recommended components component rating part number source remarks c1, input capacitor 0.1 f, 10%, 16 v, x5r or x7r ceramic capacitor (0603) grm188r71c104ka01d murata 10 v minimum rating can be used cin, input capacitor 4.7 f, 10%, 10 v, x5r or x7r ceramic capacitor (0805) lmk212bj475kg taiyo yuden cout, photoflash capacitor 330 v 100 f (or 19 to 180 f) eph-331ell101b131s chemi-con d1, output diode 2 x 250 v, 225 ma, 5 pf bav23s philips semiconductor, fairchild semiconductor r1, r2, fb resistors 150 k each 1 / 4 w, 1%; 1206, 0805, or 0603 resistors rated for 150 v instead of two resistors, a single 300 k resistor with 350 v rating can be used r3, fb resistor 1.2 k 1 / 10 w 1% (0603 or 0402) t1, transformer l p = 14.2 h, i p = 2 a, n = 10 t-15-154m tokyo coil suitable for i lim from 0.55 to 1.75 a l p = 7.4 h, i p = 2 a, n = 10 t-16-103a tokyo coil suitable for i lim from 1.2 to 1.75 a only l p = 12.8 h, i p = 1.5 a, n=10 t-16-024a tokyo coil suitable for i lim from 0.55 to 1.4 a only
photoflash capacitor charger with programmable current limit and igbt driver A8835 14 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com package ej, 10-contact tdfn with exposed thermal pad 2.38 10 10 2 1 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-229weed) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 son50p300x300x80-11weed3m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) b pcb layout reference view 1.65 2.38 0.30 1 10 0.50 0.85 3.10 c 1.65 c 0.08 11x c seating plane d 0.25 +0.05 ?0.07 0.50 0.75 0.05 3.00 0.15 3.00 0.15 0.40 0.10
photoflash capacitor charger with programmable current limit and igbt driver A8835 15 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com copyright ?2008-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 1 april 19, 2012 miscellaneous format changes

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